Here are two numbers that don’t want to sit in the same room. A research effort called Fengshui reports that a pool of just eight co-optimized chiplets delivers a 48.5% reduction in energy. Meanwhile, the framing at Chiplet Summit 2026 for Dr. Nasrullah’s talk wasn’t about shaving halves off anything — it was about AI’s 10GW challenge. Cut your energy in half and you still have a five-gigawatt problem.
That tension is the whole story of chiplet co-design right now, and it’s why I keep circling back to it. The gains are real and measurable. The target keeps moving faster than the gains.
What’s actually being claimed
Let me separate the signal from the vendor deck. A few concrete things exist:
- A University of Michigan technical paper (dated September 19, 2026) on a chiplet co-design framework that reduces energy and design costs for AI accelerators.
- An open benchmark for evaluating AI thermal models in 2.5D packaging.
- The Fengshui work on bespoke chiplet ecosystems, with that eight-chiplet pool spanning different dataflows, processing-in-memory, and network switches.
- Dr. Nasrullah’s Chiplet Summit framework, described as four techniques, the first of which is node mixing.
- The U.S. CHIPS National Advanced Packaging Manufacturing Program, which explicitly names chiplet ecosystems and co-design as in scope.
- Commercial tooling, notably Cadence’s Chiplet Platform Solutions.
Note what that list is and isn’t. Five of six items are research papers, conference talks, benchmarks, or public funding programs. One is a shipping commercial platform. That ratio tells you where this technology sits on the maturity curve.
About those Fengshui percentages
The reported figures are 48.5%, 88.1%, 93.0%, and 97.8% reductions across energy, an energy-derived composite, EDP, and an EDP-derived composite. I want to be straight with you: in the source material I’ve seen, the metric labels past the first one are mangled by formatting. The 48.5% energy number is clear. The others are composite metrics — energy-delay product and variants — and composite metrics compound. A 97.8% reduction in a product of two improved terms is arithmetically unremarkable and rhetorically enormous. Both things are true at once.
This is the kind of thing I flag every time I review an AI tooling claim. Not because the researchers are being dishonest — they labeled their axes — but because the 97.8% is the number that ends up in a slide deck, stripped of the word “EDP,” three months later.
Why co-design is the interesting part
The word doing the heavy lifting here is co-design, not chiplet. Chiplets by themselves are just disaggregation — you break a monolithic die into pieces, you get better yield and more mix-and-match freedom, and you pay for it in interconnect energy and thermal headaches. That trade has been understood for years.
Co-design means the accelerator architecture and the physical partitioning get decided together rather than in sequence. Node mixing, the first of Nasrullah’s four techniques, is a clean example: put logic on an advanced node where density pays off and keep I/O or analog on a mature node where it doesn’t. You only get that choice if someone decided the partition boundaries with the workload in mind.
The Fengshui result makes the same point from the other direction. Eight chiplets, chosen to cover different dataflows plus PIM plus switching, is a small library. The win comes from the pool being co-optimized, not from the pool being large. That’s a design-cost argument as much as an energy one — a small reusable library beats a bespoke die per product.
What this means if you’re not a chip designer
Most of you reading agntbox aren’t taping out silicon. So why care?
Because inference cost is downstream of this, and inference cost is the line item that decides which AI features survive contact with a budget. The 10GW framing isn’t abstract — it’s the reason your API pricing looks the way it does. Every percentage point that co-design claws back at the package level eventually shows up as headroom somewhere in your stack.
The honest caveat: that transmission takes years, and it’s lossy. Research frameworks from September 2026 don’t appear in the accelerator you rent next quarter. The open thermal benchmark for 2.5D matters precisely because thermal behavior is where paper gains go to die — stacked and side-by-side dies trap heat in ways monolithic dies don’t, and a design that’s efficient on paper can throttle in a rack.
The public funding piece is the part I’d watch most closely. CHIPS money explicitly covering chiplet ecosystems and co-design is what turns scattered papers into shared standards and interoperable libraries. Without that, every vendor builds a private chiplet zoo and the reuse argument collapses.
My read
Chiplet co-design is one of the few AI efficiency stories where the mechanism is legible and the measurements are specific. I’ll take a labeled 48.5% over a vague promise of better performance per watt any day. Just hold the composite-metric numbers at arm’s length, and keep the 10GW figure in view — it’s the reason halving energy is necessary and still not sufficient.
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