Seven years. That’s roughly the gap between now and the window ASML has penciled in — 2031 to 2033 — for fixing a limitation that already bites the biggest chip designs on Earth: its $400 million lithography machine cannot print them in a single exposure.
I review tools for a living. Mostly software, mostly AI toolkits, mostly things that cost less than a used car. But the pattern I keep running into at the top of the semiconductor supply chain is the same pattern I run into with agent frameworks and dev platforms every week, just with six more zeros attached. The spec sheet is stunning. The workflow around the spec sheet is where the pain lives.
The stitching tax
When a machine can’t expose a full design in one shot, you split the design and print it in multiple steps. That’s not a rounding error in cost or complexity — it’s extra passes, extra alignment, extra chances for something to go slightly wrong across a boundary that shouldn’t exist in the first place. Every one of those steps is time on a tool that costs $400 million and has a queue behind it.
AI accelerators are precisely the designs that push against this ceiling. They’re enormous. They want more area, more of everything, and they want it now. So the workload that’s driving the most demand for these machines is also the workload that most reliably runs into the machine’s hardest constraint. Demand and limitation are pointed at each other.
Why the fix takes until the 2030s
This is the part that reframes the story for me. A software vendor with a known limitation ships a patch in a quarter. ASML’s answer arrives in the early 2030s, because the fix isn’t a config change. It’s optics, physics, and a manufacturing ramp that has to be built before it can be sold.
And near-term output isn’t gated by ambition either. It’s gated by physics and clean-room space. You cannot cloud-scale a clean room. There’s no elastic tier. ASML’s 2026 plans call for something on the order of 65 Low NA EUV systems and roughly 130 DUV immersion systems, with a planned capacity increase on top of that. Those are not numbers you nudge upward with a sprint.
Meanwhile, CFO Roger Dassen told Reuters that ASML’s existing EUV machines — the roughly $200 million class — are effectively sold out through 2027. Sold out. On a multi-hundred-million-dollar capital tool. Try to imagine the equivalent in any other market.
The customers are buying anyway
Here’s what makes the limitation interesting rather than damning. On 8 September 2026, ASML said Samsung Electronics and TSMC had committed to using its High NA EUV systems in high-volume production. Intel has given the platform its own vote of confidence. These are the most cost-sensitive, physics-literate buyers in existence, and they’re signing up for a tool with a known gap and a fix years out.
That tells you what the alternative looks like. When the best tool in the category has a documented weakness and the customers still queue for it, the weakness isn’t a dealbreaker — it’s the price of admission. I say the same thing about a few AI toolkits I’ve panned on specifics and still recommend on balance.
What this actually means if you build on AI hardware
You are not buying these machines. But you are downstream of them, and the constraint shows up in your world as three things:
- Compute prices that don’t fall on a software curve. Multi-step exposure adds cost at the very bottom of the stack for exactly the chips you want. That cost doesn’t evaporate because your inference bill grew.
- Supply timelines measured in years, not releases. Sold out through 2027 means the accelerator roadmap you’re planning against is already largely fixed.
- Design workarounds becoming normal. Chip architects have been splitting big designs into pieces and connecting them for a while now. Expect that style of engineering to keep shaping what the hardware you rent actually looks like.
The reviewer’s read
I’ve stopped treating “this tool has a real limitation” as a verdict. What matters is whether the limitation is honest, bounded, and on someone’s roadmap. ASML’s is all three. It has published a window. It has named the constraint. It hasn’t pretended clean-room space is a solvable marketing problem.
Compare that to most of the AI tooling I test, where the limitation is discovered on day nine of a pilot and the roadmap is a Discord message. A seven-year fix timeline with a clear explanation beats a two-week fix timeline that never arrives.
The uncomfortable part is what happens in the gap. For the rest of this decade, the most in-demand chips in the world get built on a tool that can’t quite print them in one go, on a production line that can’t grow much faster than the buildings holding it. That’s the constraint everything else in AI is currently balanced on, and no amount of funding rewrites the physics before the optics are ready.
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